217-234pp.
Guest Editorial
Introduction to the Special Issue: Nano MVL Structures
Svetlana N. Yanushkevich and Vlad P. Shmerko
abstract
full text
235-248pp.
Minimization of Ternary Reversible Logic Cascades Using a Universal Subset of Generalized Ternary Gates
Erik Curtis and Marek Perkowski
abstract
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249-266pp.
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa and Yasuo Takahashi
abstract
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267-277pp.
Multiple Path Switching Device Utilizing Size-Controlled Nano-Schottky Wrap Gates for MDD-Based Logic Circuits
Seiya Kasai, Tatsuya Nakamura and Yuta Shiratori
abstract
full text