Impact of Design Parameters on 6T and 8T SRAM Cells at 45nm Technology
Joshika Sharma and Shyam Akashe
A SRAM cell is designed to meet the requirements for operation in nano ranges. SRAM is highly used circuits in memory chips as it is used in caches, FIFO, register files etc. The scaling of CMOS technology can cause a significant effect on SRAM cell such as leakage current, leakage power and delay etc. In this paper we propose a novel design of Static Random Access Memory for 8T SRAM cell for high speed operations, and we use two voltage sources connected to Bit line and Bit bar line for write and read operation. Simulation results confirmed that proposed 8T SRAM cell has improved parameters for write operation of leakage current is 69pA, leakage power is 7.581nW and delay is 20.55ns and for read operation of leakage current is 53.90pA, leakage power is 1.709μW and delay is 21.44ns as compared to 6T SRAM in 45 nm technology.
Keywords: SRAM, CMOS, leakage current, leakage power, delay, read and write operation.