Pragmatic Performance Analysis Among Different DRAM Memory Cells
Tarushree Varshney, Shyam Akashe and Saurabh Khandelwal
This paper proposes DRAM (Dynamic random access memory) for 3T DRAM (3 transistors dynamic memory), 4T DRAM (4 transistors dynamic memory) and 3 transistors with a Gated Diode DRAM cell for nanoscale technology. Using DRAM, many advanced processors now on chip instructions and data memory. But major contribution of power dissipation in DRAM cell is off-state leakage current. The main motive of the present paper is to reduce the consumption of power as well as to reduce the leakage of current and leakage of power. 3T1D is a non destructive read DRAM cell with three transistors (T) and a gated diode (D) which acts as a storage device and an amplifier. Here, three circuits of DRAM (such as 3T DRAM cell, 4T DRAM Cell, and 3T1D DRAM cell) have been taken and comparison among them was observed which resulted that 3T1D DRAM cell offers faster read speed and less read leakage current than conventional 3T DRAM and 4T DRAM. The average power consumed by 3T1D in nW (nano Watt) whereas 3T DRAM and 4T DRAM in micro Watt. 3T1D offers 36% less leakage current than 4T DRAM and 77% less leakage current than 3T DRAM. Read and write operation for single bit storage of DRAM circuits are shown by simulating on CADENCE TOOL for 45nm (nano meter) technology.
Keywords: Low Power, Dynamic RAM, Nanotechnology, CMOS, Leakage current, Leakage power, 3T1D DRAM.