Estimation of Leakage Reduction in FinFET Based Schmitt Trigger by Applying SVL Technique
Pawan Sharma, Saurabh Khandelwal and Shyam Akashe
Today’s Scenario faces a great demand to design a low power and highly stable Schmitt trigger circuit. Leakage power is becoming an essential parameter and requires focus attention in designing VLSI circuits & systems. This brings us to evaluate new techniques for leakage reduction in order to improve the performance of the design. Schmitt Trigger (ST) plays a significant role to reduce noise in the field of digital world, but as technology scales down to nano-meter domain, leakage current, power and delay limits the operation of Schmitt trigger for low power applications. It has been observed that 30-40% of the total power of the Schmitt Trigger is dissipated due to the leakage from the transistor. This paper proposes a new technique using three different mechanisms to reduce the static leakage current, delay and total dissipated power from the FinFET based Schmitt trigger and conventional 4T CMOS based circuit. In first technique, the supply voltage is decreased (USVL). In the second techniques the voltage of the ground node is increased (LSVL). Furthermore, combined technique (USVL plus LSVL) is also applied over the FinFET design. Implementation of USVL and LSVL to FinFET based Schmitt Trigger offers leakage power of 2.208 pA and 2.194 pA respectively at 0.8 volt reference supply voltage. Result obtained show that reductions in the circuit delay along with total dissipated power are also achieved.
Keywords: Leakage power, delay, FinFET, Upper SVL, Lower SVL.