Leakage Control Transistor (LECTRA): A novel Approach for Leakage Reduction in Low Power VLSI Design
Sankit R Kassa and R. K. Nagaria
A new circuit approach is proposed in this paper to reduce the sub threshold and gate oxide leakage power consumption in low power VLSI circuit design. This approach is useful in reducing leakage currents in active as well as standby modes of operation. Here two extra transistors are added one of which is high threshold voltage transistor and the other one is low threshold voltage transistor. High threshold voltage transistor is used as a primary device to reduce the leakage currents and for maintaining the performance of CMOS circuit. A low threshold voltage transistor is configured as a sleep transistor with PDN. Experiments conducted on a proposed circuit design using 180nm, 130nm, 45nm and 22nm TSMC ® using Tanner EDA tool. Results obtained shows significant reduction in leakage power when compared to well-known design approaches.
Keywords: Deep submicron, Sub threshold leakage current, Standby and Active mode, Gate oxide leakage current, power optimization