Analysis of FinFET Based 8T SRAM Cell Using Adaptive Voltage Level Techniques
Joshika Sharma, Saurabh Khandelwal and Shyam Akashe
The use of FinFET based Static random access memory (SRAM) is effectively increasing due to its features which reduces the cell leakage and improve the cell stability. Also, the reduction of cell leakage power is very important for low power applications. The main contributor of total power consumption of the circuit is high leakage currents. We have investigated that CMOS technology have limited control over the short channel effects, due to this high junction leakage caused by band to band tunneling and increased in threshold voltage fluctuations creates problem at every technology node. This paper discloses the analysis of different parameters of FinFET based 8T SRAM cell with leakage reduction technique like AVL (Adaptive voltage level) apply in FinFET based SRAM cell during write operation. Simulation results are performed on cadence virtuoso tool at 45nm technology. The result are compared, we can say that there is significant reduction in leakage for this proposed cell using AVL technique.
Keywords: FinFET, SRAM, AVL technique.