Optimization of Leakage Current and Leakage Power on 4×4 Array with SVL Technique Employed 7T SRAM Cell in Nanometer Regime
Shalini Singh and Shyam Akashe
In this era, 2D scaling of various electronic appliances both the logic circuits as well as the memory based devices is eventually reaching their fundamental limits because of aggressive scaling. But as we move on from one technology generation to the other leakage is increasing to an unavoidable extent. Consequently identification and simulation of various leakage contributing components has become an important factors for estimating different leakage parameters and thus increases the alarming need for simulating it with different leakage reduction techniques. In this paper we have investigated different self controllable voltage level (SVL) circuits in 7T SRAM cell and then have been implemented in 4×4 array. This technique is a power saving model which provides maximum supply voltage during active mode and minimum supply during standby mode. The circuit has been simulated at different supply voltage of 1V, 0.7V, 0.5V and 0.3V and the results has been verified using cadence virtuoso tool in 45nm technology.
Keywords: Array, SRAM cell, SVL, Leakage current, Low power, VLSI, Logic circuit