Optimization of Leakage Parameters of FinFET Based 6T SRAM Cell Using LECTOR Technique
Vishwas Mishra and Shyam Akashe
In this paper we introduced a technique named LECTOR that is applied to FinFET based 6T SRAM cell that significantly lowers the leakage current without hampering dissipated power which is dynamic in nature, rather decreases the static power and leakage current to a great extent. Today there is a great demand of high performance and low leakage driven devices. Along with these features designers are plunging towards sub-micron level to manufacture high density devices. But all these design factors have led to increase in sub-threshold current, due to reduction of gate oxide thickness and hence power dissipation also increases. So, this paper presents the design and verification of conventional and LECTOR technique employed FinFET 6T SRAM cell at 0.5V, 0.7V and 1V in Cadence Virtuoso Tool at 45 nm technology. It is observed that leakage current reduces to 39.03 fA from 66.19 fA which is about 41.03% less at 0.5V that shows that technique employed cell can be used till 0.5 V at 45 nm technology.
Keywords: 6T SRAM, LECTOR, leakage current, power dissipation.