Low Power Subthreshold Voltage Level Shifter Design Using SVL Technique
Rashmi Sharma, Shyam Akashe and Ravi Shrivastava
The low power and low leakage in voltage level shifter is presented in this paper. With the aim of reducing the leakage power of CMOS devices, during digital circuit construction obligatory low supply voltages and low power consumption. In the digital circuits leakage power is leading factor, which is mainly influenced to the power consumption. For low power applications, A reduction in leakage power is important. High leakage currents are the major giver of total power consumption of the CMOS circuit. Advance in technology, the traditional CMOS technique is compared with the self-controllable switch (SVL) technique. Various leakage reduction techniques are employed for reduce leakage and power, SVL technique is one of them leakage reduction technique. In order to achieve power consumption and power dissipation, a self-controllable voltage level switch is used in proposed method. Simulation is done by using cadence virtuoso environment at various supply voltages (0.3 to 1.2 V). By using this leakage optimization technique in voltage level shifter, 89% leakage power is reduced as compared to power gating technique.
Keywords: Multi-supply voltage design, Level Shifter, Low power, SVL technique CMOS.