Square Root and Inverse Square Root Computation Using a Fast FPGA Based Architecture
Abul Hasnat, Atanu Dey, Santanu Halder and Debotosh Bhattacharjee
In this work, a fast FPGA based architecture is proposed to compute square root and inverse square root. Here seven new base numbers are introduced for faster computation of square root and inverse square root using Quake’s algorithm. The FPGA based architecture is synthesized on Xilinx Virtex 5 XC5VLX85T-3FF1136 FPGA kit simulated on Model- Sim 6.2c using VHDL. The proposed system gives accuracy for the computed Square Root and Inverse Square Root values up to 12 bits in all cases for IEEE754 single-precision floating point number input. The proposed architecture gives result in twelve clock cycles only (for computation of core) at the frequency of 194.122 MHz to compute both of Square Root and Inverse Square Root values. The architecture works faster than the recently reported studies in the literature.
Keywords: FPGA, Square Root, Inverse Square Root, Magic number, Quake’s algorithm