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Memristor Based MAC Architecture Design For (2n − 1) and 2n Radix
Arindam Banerjee, Sohini Pal, Swapan Bhattacharyya and Debesh Kumar Das

Memristor based Multiply and Accumulate (MAC) architecture for radix (2n − 1) and 2n have been reported in this paper. Memristor technology is an emerging field in the processor design technology. Here the functional components of the proposed multipliers for the MAC structure such as partial products, adder etc. have been designed using IMPLY gate which is the first building block implemented using memristor. In memristive logic family, each memristor acts as an input, output, computational logic element in computation process. The main contribution of this paper is to show the design methodologies for modulo addition and multiplication for (2n − 1) and 2n radix and MAC architecture using these multipliers and adders and then the techniques have been implemented using memristor. All the basic building blocks, which have been presented here, have generic structures for n bit with radix (2n − 1) and 2n. We have calculated the memristor count for the MAC structures to estimate the latency of the design. The implementation scheme is new and beyond the scope of comparison with other literature reported so far.

Keywords: Memristor, logic family, modulo multiplier, multiply and accumulate (MAC).

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