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An Approach for Low Power Circuit Design Using Low Threshold Transistors
Shams Ul Haq and Vijay Kumar Sharma

Leakage power has become a more dominating component of total power consumption in battery-operated portable systems. Leakage control techniques are applied at circuit level as well as at architectural level. Multi threshold CMOS (MTCMOS) is used at circuit level in Integrated Circuits (IC’s) to reduce the leakage power by shutting off currents to logic blocks that are not in use. Resistance offered by high threshold voltage (Vth) sleep transistor during active mode should be small enough. The total standby leakage in the chip is proportional to width of sleep transistor and other related dimensions. Optimal sizing of sleep transistors is difficult. MTCMOS circuits suffer from drawbacks like long wakeup latency, large amount of rush-through current and wasteful energy usage during mode transition from standby to active and vice versa. An energy-efficient high-speed low power low Vth CMOS logic is proposed for designing low power circuits. The scheme is implemented using Mentor Graphics’s tools followed by comparison with the already existing leakage control techniques.

Keywords: Nanoscale regime, leakage power, CMOS; MTCMOS, sleep control transistor, full adder

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