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A Low Power Reduced Latency MC-CDMA Receiver
Sajad A. Loan, S. N. Ahmad, M. Usaid Abbasi and Humyra Shabir

A low power with reduced latency algorithm for multi-carrier CDMA receiver is proposed. The proposed algorithm treats the received signal as block of symbols. The number of multiplications taking place in the combiner circuit of the receiver architecture of MC-CDMA has been reduced from M-multiplications for an M-block of symbols for a single carrier signal to a single multiplication for M-blocks. Hence there is the reduction of (M-1) multiplication operations which results in reduction of power consumption and enhancement in speed of operation. It produces a power reduction of great deal more than 50% and comparatively much lower processing delay. In this algorithm improvements in FFT block in the conventional design is also proposed. A novel coefficient ordering based low power pipeline radix-4 FFT processor is used which results in power reduction and enhancement in the speed of operation.

Keywords: Low power, Latency, FFT, CDMA.

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