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Process Variation Issues in VLSI Interconnects-A Case Study
K. G. Verma, Brajesh Kumar Kaushik and R. Singh

This research paper provides a comprehensive overview of the types and sources of all aspects of process variations in driver –interconnect-load system. The impacts of these interconnect process variations on circuit delay are discussed. Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement Technology (RET). Process variations manifest themselves as the uncertainties of circuit performance, such as delay, noise and power consumption. Environmental variations, such as supply voltage and temperature variations, also impact circuit delay and noise. Transistor performance depends heavily on gate and other dimensions. A 10% transistor gate variation can translate to as much as a variation of -15% to +25% in gate delay. Interconnect parasitics are significant and complex components of circuit performance, signal integrity and reliability in IC design.

Keywords: Process variation, interconnects.

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