Design of a 1- Bit Full Adder for the Reduction of Power and PDP Using Pass Transistors
Deepak Bhatnagar and Mohammad Arif
Demands for the low power VLSI circuits have been pushing the development of design methodologies to reduce the power consumption drastically. To meet the growing demand of power minimization; we propose a new hybrid full adder design. The schematic diagram of this new adder circuit is made using Mentor’s Design Architect and tested with ELDO simulator. Simulation results show that our approach is saving 99% power at the cost of small delay overhead than the conventional adders. But power saving overweighs the increase in delay and finally we have obtained a lower power delay product.
Keywords: Full Adder, Pass Transistor, Power Consumption, Power Delay Product (PDP)