Performance Evaluation of FinFET Based 6T and Gated Ground 7T SRAM Cell’s
Ravindra Singh Kushwah, Saurabh Khandelwal and Shyam Akashe
In this paper, we illustrate the designing nanoscale FinFET based 6T and gated ground 7T Static Random Access Memory (SRAM) cells. The Fin- FET can be used to improve the performance and reduces the short channel effect, leakage current and the power dissipation. SRAM cells are integrated the same chip with the processors. SRAM cells consume large percentage of a chip area and therefore leakages give static power dissipation. The aim of this paper is to improve the speed, leakage current and leakage power of 6T and gated ground 7T cells using FinFET in 45nm technology. In this paper represents the simulation of 6T and gated ground 7T SRAM cells and analysis of different parameters such as speed, leakage current and leakage power. These simulation results are carried out on Cadence Virtuoso Tool at 45nm Technology.
Keywords: FinFET, Leakage current, leakage Power, Read Time, Static random access memory (SRAM), Write Time