Low Power SRAM cell Design Using Independent Gate FinFET
Vandna Sikarwar, Saurabh Khandelwal and Shyam Akashe
In this paper, 6T SRAM has been designed using Independent gate DG FinFET in which both the opposite side gates can be controlled independently. Independent control of front and back gate in Double gate devices (FinFET) can be effectively used to improve performance and reduce power consumption. Leakage current degrades the performance of CMOS devices, so that leakage reduction technique is used in this paper, which sufficiently reduces the leakage current and hence power consumption is reduced. Multi threshold voltage leakage reduction technique has been used in which high threshold voltage (VTH) device is used as the sleepy transistor which provides virtual supply or virtual ground to the SRAM cell. Short channel effect such as DIBL has been observed in independent gate FinFET transistor. Some parameters like leakage current, leakage power and power consumption have also been observed.
Keywords: SRAM cell, CMOS, FinFET, leakage current, leakage power