Efficient Design and Implementation of 21T Ternary Full Adder Based on Capacitive Threshold Logic and CNTFETs
V.N.V. Satya Prakash, B. Uday Kumar, S. Sowmya Sree, E. Suneel, C. Sai Charan and Ramaswamy T.
Design and implementation of a 21-transistor (21T) ternary full adder based on carbon nanotube field-effect transistors (CNTFETs) and capacitive threshold logic (CTL) are described here. Extending the conventional binary logic to three digits (0, 1, and 2), the ternary logic system possesses greater information density and energy efficiency over the conventional binary logic. The ternary full adder is small in size and low power consumption because it employs CTL, which is based on capacitive devices to establish logic levels. This makes it an ideal option for upcoming tiny-scale electronics. The performance of the ternary full adder is also enhanced with the use of CNTFETs. Currently, digital circuits are facing challenges in becoming faster while consuming less power. This is comparable to faster speed and power saving at lower technology nodes. Cadence CNTFET environment, an expert software tool for CNTFET-circuit model, models the complete adder circuit. Simulation outcomes confirm how economical the 21T structure is, with area, power, and delay advantages. In the design of Capacitive Threshold Logic as an effective approach to high-performance, low-power arithmetic calculations in future computing systems, this paper brings ternary logic systems to the verge of reality under the scenario of CNTFET technology. The proposed design is the foundation for investigation of ternary logic in future digital systems based on CNTFET and as a proof of concept of ternary logic circuits.
Keywords: 45-nm CNTFET, look-up tables (LUTs), RTL (Register-Transfer Level) design, capacitive threshold logic and synthesis