High-Speed VPAC with Low Hardware Complexity for Efficient ADPLL Applications
Sehmi Saad, Afef Kchaou, Aymen Ben Hammadi and Hatem Garrab
This paper presents a novel topology for the phase counter used in All-Digital Phase-Locked Loop (ADPLL) architectures, specifically optimized for high efficiency and performance in wireless communication systems. The proposed circuit, known as the Variable Phase Accumulator (VPAC), operates as a digital component at the highest frequency within the ADPLL. By leveraging count accumulation referenced to the lower-frequency domain, the VPAC enables high-speed operation while efficiently processing the oscillator’s high-frequency output, with reduced circuit complexity.
The design significantly shortens the timing-critical path and minimizes hardware logic in the high-frequency domain by incorporating a compact shift register that encodes only four distinct states. A simple logic gate is used to manage the counting process, thereby reducing power consumption without compromising performance. Implemented in a 90 nm CMOS process, the proposed VPAC achieves up to a 20× improvement in power efficiency compared to conventional counter architectures, without incurring penalties in silicon area or operating frequency. This architecture offers an effective balance of speed, area, and power, making it highly suitable for low-power, high-performance transceiver systems and System-on-Chip (SoC) integration in next-generation wireless applications.
Keywords: VPAC, high speed counter, ADPLL, retiming clock, radio frequency