Ultra Low Voltage Body Biasing Adder Schemes for Significant Signal Processing Arithmetic Circuits at Near Threshold Computing
Chakali Chandrasekhar, Sari Mohan Das, S. Jayachandranath, Sk. Umar Faruk, V. Jayaprakasan and Mohammed Mahaboob Basha
A novel approach Gate Level Body Biasing (GLBB) for mirror full adder is explored in the realm of near threshold ultra-low voltage logic designs. A mirror-full adder was constructed with standard 45nm CMOS technology for testing purposes. Compares traditional zero-body biased CMOS and MOSFETs with DTMOS circuits under various operating conditions. Post layout simulations indicate that, for leakage-related power usage scenarios, the GLBB method provides significant reductions in both energy requirements per operation and delay when compared to traditional CMOS and DTMOS techniques. From the experimental results, the recommended sub mirror full adder outperforms with existing models. The proposed adder, for instance, yields a PDP and EDP of 0.348 aJ and 0.013 yJs, whereas other efforts yield more energy consumption in comparison to the adders in the literature. The area requisite by this proposed complete one bit adder may be half that needed by DTMOS designs but more when compared to standard CMOS designs.
Keywords: Body biasing, leakage current, sub threshold, NTC, energy, EDP efficient