Implementation of Dynamic Triple Modular Redundancy in Fault Tolerant System
V.N.V. Satya Prakash and A.Haritha
Over the years, significant work has been done on high-integrity systems, such as those found in vehicles, satellites and planes, in order to reduce the probability that a logic fault triggers a failure in a system, hence having functional safety as a primary requirement. This work introduces the architecture and conceptual analysis of an Enhanced Dynamic Triple Modular Redundancy (DTMR) system, with emphasis on its novel hardware-level techniques for real-time fault detection, anticipatory data correction, and accurate physical isolation of chronically faulty modules. Fault-tolerant processing is necessary in safety-critical applications like aerospace, automotive, and industrial control, where permanent and transient faults undermine system reliability. Transient and permanent faults from modern semiconductor scaling impose severe reliability threats, requiring advanced fault-tolerance schemes with reasonable overheads. In contrast to traditional static TMR or architecture-level dynamic redundancy schemes, our outlined Enhanced DTMR incorporates a threshold-dependent fault counter for dynamic high-impedance (Z-state) isolation of faulty processing units. A special fault corrector actively corrects data streams from known faulty units before final voting, enhancing systemwide overall reliability and reducing recovery latency. Conceptual analysis reveals that this method achieves better fault mitigation rates with optimized hardware resource usage and low performance overhead, making it a viable option as a high-integrity, power-constrained embedded system.
Keywords: DTMR, fault tolerance, FPGA implementation, high-Z isolation, interleaved threads, triple modular redundancy, verilog, voter logic