Scalability Analysis of AMP LEON3 Multicore Systems on Xilinx FPGAs Using AES as a Benchmark Workload
Afef Kchaou, Sehmi Saad and Hatem Garrab
This work investigates the hardware scalability and FPGA resource trade-offs of mono-, bi-, and quad-core LEON3 processor configurations implemented on a Xilinx Virtex-5 FPGA under an Asymmetric Multi-Processing (AMP) model. Using the Advanced Encryption Standard (AES) as a representative compute-intensive benchmark, we evaluate how multicore replication impacts logic utilization (slices, LUTs, BRAM), interconnect complexity, and system-level throughput. Results show that while quad-core LEON3 achieves a 30.9% increase in realtime task throughput for parallelizable workloads (e.g., AES encryption), it consumes 95% of available FPGA slices, revealing a steep hardware cost for marginal gains in non-parallelizable tasks (e.g., AES decryption). Critically, the non-coherent AMBA AHB bus and private cache architecture impose minimal inter-core interference, as evidenced by stable CPI across configurations. This study provides hardware designers with empirical data on the area-performance trade-offs of scaling soft-core multicore systems in resource-constrained FPGA fabrics, particularly relevant for radiation-tolerant embedded devices in aerospace and defense applications.
Keywords: Multicore scalability performance, FPGA resource utilization, Advanced Encryption Standard (AES), LEON3, Asymmetric Multi-Processing (AMP)