Design Exploration of Threshold Logic in Memory and Experimental Implementation Using Knowm Memristors
Carlos Fernandez, Albert Cirera and Ioannis Vourkas
In the context of computing in resistive memories (ReRAM), the implementation of threshold logic gates (TLGs) with memristors has been especially investigated for programable in-memory logic implementations. In this work we focus on two circuit design concepts for threshold logic with memristors: the voltage divider and the voltage adder. We provide an analytical exploration of the impact of the HRS-to-LRS ratio of memristors on the performance of every circuit and highlight the advantages of the voltage adder approach. Through experimental results from a proof-of-concept circuit, implemented using self-directed channel (SDC) memristors by Knowm Inc., we validated the conclusions derived from the theoretical analysis for computational memory structures supporting threshold logic gates. Moreover, we present the design and simulation of a bitline driver and sensing circuitry for a 1T1R array, where the proposed threshold logic scheme can seamlessly fit, thus providing solutions towards the development of robust and reliable computational ReRAM modules.
Keywords: Memristor, resistive switching, resistive RAM, ReRAM, in-memory computing, NOR logic, Knowm, SDC memristors