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Comparative Analysis of MTCMOS and SVL Based Flip Flop Design
Pooja Joshi, Saurabh Khandelwal and Shyam Akashe

This paper elaborates high speed and low power consumption circuit for flip flop with very less number of active transistors. Flip Flops are digital data storing elements which suffers with severe short channel effects whenever scaled down to improve density in an integrated circuits. Leakage current causes the device to malfunction so we have employed the multi threshold and the self voltage level technique on the conventional CMOS structure of flip flop which have resulted to reduce the leakage current effectively in scaled down devices. We performed a comparative analysis of stand-by-leakage current, delay, temperature effect, slew rate variation and noise voltage on cadence virtuoso tool at 45 nm regime for MTCMOS and SVL based delay flip flop. The leakage power and delay of CMOS based flip flop using SVL technique is 54% and 23% lower than simple CMOS based flip flop whereas the total leakage power and delay of CMOS based flip flop using MTCMOS technique is 52% and 51% lower than the simple CMOS based flip flop circuit.

Keywords: Leakage Current, Delay, Slew Rate, Noise, MTCMOS, SVL, DFF (5T)

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