Diminution of Dissipated Power and Leakage Current by Employing FinFET Based Opamp for 45nm Regime
Shobhna Ferwani, Saurabh Khandelwal and Dr. Shyam Akashe
As CMOS devices are shriveling to nanometer regime, increasing the consequences in short channel effects and variations in process parameters. It leads to cause the reliability of the circuit also the performance. To solve the issues of CMOS devices, Fin-FETs are considered as a promising candidate for today’s electronic devices for low-voltage digital and analog circuit application. In this paper, we adduced a low-voltage two stage operational amplifier (OP-AMP) based on emerging Fin-FET technology. The proposed Fin-FET based operational amplifiers performance characteristics are studied and compared with the existing CMOS technology at 45nm scale. The opamp performance characteristics are obtained by employing Cadence Virtuoso tool for circuit simulation at 0.9V input supply voltage. The low leakage current, low parasitic resistance and high current driving abilities of the Fin-FET technology are taken into realization with basic analog building block opamp circuit. The benefit of employing Fin-FET rather than CMOS technique is the significant reduction in power consumption. Furthermore, by employing Fin- FET technology the improvement in slew rate has been significantly achieved. The settling time also has been improved from 0.099μs to 0.094μs. The simulation results are given and concluded.
Keywords: Two stage opamp, CMOS vs. Fin-FET, power dissipation, and Leakage current