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Reduction of Single Event Latch-up Using FinFET Based 7T SRAM Cell
Varun Sable and Shyam Akashe

Memory is the essential part of System on Chip applications. The analysis of memories is not an easy task to calculate any parameter in a single step. Tools are operated on a standard basis. It neglects all the issues of the device either it may be a MOSFET or a BJT or any emerging device. All tools provide standardized devices but they do not include following issues like sub threshold leakage, punch through, body effect and latch up in inverters. In any circuit when we scale down the technology then, all effects are taken into account. The parasitic diodes are inherent between the n-well and p-substrate or p-well and n-substrate all to be the latch up occurrence in this System on Chip. Latch up failure mainly occurs and find out only on output pin of the IC. In memories, latch up effects gives effective degradation in data mostly in hold mode. In this paper, we calculated the reduced effect of single event latch-up using FinFET based 7T SRAM Cell and this result is diminished as compare to conventional based 7T SRAM Cell.

Keywords: Latch-Up, Single Event, Short Channel Effects, FinFET, SRAM, Parasitic

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