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Analysis of Encoder and Using SVL Leakage Power Reduction Technique in Encoder
Shivam Dixit and Shyam Akashe

This paper represents the different functionality of Encoder. Encoder is a device which transforms the data from one code to another. In this paper, parameters of encoder is calculated and compared with SVL, USVL, LSVL technique used Encoder. Self Controllable Voltage Level technique (SVL) reduces the leakage power in logic CMOS circuit and this technique provides a high performance and low power design by using both low and high threshold voltage transistors. In this paper it was observed that the SVL technique used encoder consumed less total power of circuit than conventional, U-SVL and L-SVL Encoders. It was found that the total power is consumed by SVL is 2.720 nW, whereas Conventional, U-SVL And L-SVL are 29.95 nW, 3.480 nW and 3.131 nW respectively. This paper has been simulated using 45nm technology with Cadence virtuoso tool.

Keywords: Encoder, SVL, Total Power Consumption, Leakage power.

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