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A Novel Structure for 6T Schmitt Trigger Using FinFET Maneuver with EDP and PDP
Akash Yadav, Nikhil Saxena and Saurabh Khandelwal

Schmitt Trigger is to generate the digital signals by using analog signals whose remarkable use in the designing of Integrated Circuits (IC’s) that will help us to enlighten the execution of low channel lengths and provides very ultra-low power Schmitt Trigger design. The Power dissipation and delay is desirable to be minimized for better performance of CMOS based analog circuit as well as digital circuits.FinFET based structures greatly contributes to decrease the leakage power due to the fin controllability and gate observability all over the Fin design. In this paper, FinFET based Schmitt Trigger is represented which suggests the good noise voltage, Energy delay Product and power delay product which helps us to assign the range of the input supply at which the trigger circuit finally works. Our design has to obtain the considerable reduced delay values as well as the power spectre, so that the energy dissipation in the excess amount as well as power dissipation in form of heat and other parameters which are not in useful for the system behaviors in marginal range of input voltage specification.This work condenses delay and power dissipation as well as Energy delay product (EDP) and Power Delay Product (PDP) considerably as FinFET based Schmitt triggers offers an EDP and PDP reduction of 66.99 and 50.48% respectively at 0.7V power supply. The Energy delay product and Power delay product of this design is calculated on Cadence Virtuoso tools.

Keywords: FinFET, Schmitt Trigger, EDP, PDP, controllability.

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