Comparison of Leakage Current and Power in 3T DRAM Cell Using MTCMOS Technique
Shivam Kathairiya and Shyam Akashe
The objective of this paper is to compare the power consumption, leakage voltage, leakage current and leakage power of 3-T DRAM while maintaining the competitive performance .The FinFET approach and MTCMOS technique is used in 3T DRAM to compare the performance. At nano-scale FinFET is the surrogate for bulk CMOS. FinFET are double gate device, where its two gates can either be shorted for higher recital or separately restricted for low leakage or diminish transistor count. Multi-threshold CMOS (MTCMOS) is a CMOS chip which has a Transistor with multiple threshold voltage. DRAM was first invented by Dr. Robert Dennard in the year 1966. It is used in many advanced processor for chip instruction and data memory. It majorly contributes in power dissipation in off-state leakage current. In personal computers it is used as the main memory, workstations etc. The basic advantage of using DRAM is its simplicity in its structure.
Keywords: DRAM, FinFET, CMOS, Leakage power, Leakage current, Frequency, Access time, SVL, USVL, LSVL