Modern Augmented Parameters of Full Substractor Using Power Gating Technique
Aditya Sharma, Nikhil Saxena and Saurabh Khandelwal
A conventional Full Substractor using 34 transistors is presented here. In digital signal processors and microprocessors, the full substractor is not only important for additions or subtracting based digital circuits like multipliers and dividers but is also used for accessing the address in memory. For low power requirements, there is a need to reduce leakage current in Full substractor to avoid the involvement of this sub device leakage and to prepare better sub circuit of any system so that the preparatory device is not get affected by these type parameters. In this paper, SVL (self-controllable voltage level) technique is introduced for leakage current reduction and then standby leakage power reduction. Using SVL technique we can provide dc voltage supply as per requirement for load circuit in active mode and decrease dc voltage supply for load circuit in standby mode. For reduction in leakage current in standby mode there are two approaches first USVL (upper self-controllable voltage level)technique in which dc voltage supply for load circuit is decreased and another one LSVL (lower self-controllable voltage level) technique in which ground voltage supply for load circuit is increased. This paper represents that leakage current of full substractor using SVL technique is reduced by 61.8% as conventional full substractor at 0.7 V dc supply. Simulation results are performed with 45nm CMOS technology, 20ns access time and 0.05GHz frequency using cadence virtuoso tool and leakage current for all cells are compared.
Keywords: CMOS, Full Substractor, leakage Current and SVL techniques