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High Performance FinFET Based 3T DRAM with Precise Power Consumption
Shivam Kathairiya and Shyam Akashe

The objective of this paper is to reduce the power consumption, leakage voltage, leakage current and leakage power of 3-T DRAM while maintaining the competitive performance. The FinFET approach is used in 3T DRAM for high performance. At nano-scale FinFET is the surrogate for bulk CMOS. FinFET are double gate device, where its two gates can either be shorted for higher recital or separately restricted for low leakage or diminish transistor count. DRAM was first invented by Dr. Robert Dennard in the year 1966. It is used in many advanced processor for chip instruction and data memory. It majorly contributes in power dissipation in off-state leakage current. In personal computers it is used as the main memory, workstations etc. The basic advantage of using DRAM is its simplicity in its structure. By using the FinFET CMOS technology we investigate that it provide low leakage and higher performance operation by using high speed, low Vt transistor for logic cell and low leakage, high Vt of transistor which is particularly effective in sub threshold circuit. Percentage reduction in leakage voltage, current and power after using FinFET based DRAM was found to be 19.15%, 21.65% and 95.55% respectively. 0.7V power supply is used to carry out 3T DRAM cell using FinFET in 45nm.

Keywords: DRAM, FinFETs, CMOS, Leakage power, Leakage current, Frequency, Access time

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