Slew-Rate Enhancement for a Low-Power Two Stage CMOS OP-AMP in Nanometer Regime
Pragati Gupta, Saurabh Khandelwal and Shyam Akashe
The operational amplifier (OP-AMP) is the most versatile and an integral part of many analog and mixed signal circuit designs. In this paper we present a low power two stage CMOS OP-AMP with slew-rate enhancement approach realized in a standard 45 nm CMOS technology. Slew-Rate enhancement approach has been adopted to boost the rate of positive and negative slews. In proposed technique, two auxiliary circuits have been employed to the two stage CMOS OP-AMP which results in improved slew-rates of 497 V/μs (rise) and 488 V/μs (fall). The designed OP-AMP exhibits DC gain of 82 dB, phase margin of 78º and settling time of 91.4 ns. Also, we observed that the power consumption of proposed OP-AMP is very low. Auxiliary circuitry for slew-rate enhancement does not affect the other performance metrics such as DC gain, stability and power consumption. The design and optimization of proposed OP-AMP is carried out at a power supply of 0.7 V in Cadence Virtuoso tool.
Keywords: Two stage OP-AMP, Low power, Slew-Rate enhancement, Auxiliary circuits, DC gain, settling time.