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Comparator Optimization of Flash ADC
Umesh Kumar and Ashish Mishra

In this paper we present the design methodology of high speed Flash ADC by individually optimizing its various components so that the overall performance of the resulting Flash ADC is improved over traditional Flash ADC’s Together with high speed as a parameter, components are designed so that they operate with sampling frequency as high high as 70-75 MHz with lowest power consumption and operate on power supply voltage down to 2.5V for compatible with low power digital portion of the design as well as occupy less chip area. All the components are designed using the 180nm CMOS technology.

Keywords: Comparator, Residue Amplifier, DAC

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