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Design and Analysis of Low Power Memristor Based Non-volatile 4T SRAM Cell with Power Reduction Techniques
Neha Borkar and Shyam Akashe

The continuous technology scaling have recently made power reduction an important design issue for digital circuits and applications or we can say that now-a-days power dissipation in the memory circuit has become an important design consideration. To reduce the power and other related parameters we suggested to design a non-volatile SRAM(nvSRAM) cell which retains its previous state even in the condition of sudden power failure and further some power reduction techniques like MTCMOS and Gated-Vdd are also applied. The simulations were carried out for conventional Load 4T SRAM with Proposed Load 4Transistor 2Memristor SRAM Cell ( Load 4T 2M) and techniques which shows significant reduction in parameters like Power consumption reduces 662.2 pico-Watt (pW)(conventional circuit) to 654.8 pW (proposed circuit) and goes to 568.3 pW (gated-Vdd). The propagation delay reduces from 21.22nS to 480.6pS when techniques are applied. Thus, we can say that memristor- based technology provide higher utilization, much better scalability, improvement in power, performance and cost and also overall low power consumption.

Keywords: Memristor, Memristance, Non-volatile SRAM, Power Reduction, MTCMOS, Gated-Vdd

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