Dynamic Power Dissipation Analysis in CMOS VLSI Circuit Design with Scaling Down in Technology
In this paper, dynamic power dissipation in CMOS VLSI circuit is analyzed with scaling down in technology. Dynamic power dissipation of a CMOS full adder circuit is observed in different technologies (1.200μm, 0.800μm, 0.600μm, 0.250μm, and 0.120μm). This power dissipation reduces with the scaling down in technology and reduction in the supply voltage. Microwind ver. 3.1 EDA tool is used for the layout design and simulation of the CMOS full adder circuit.
Keywords: Dynamic power dissipation, CMOS full adder, Scaling down, technology.