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A Fast and Reduced Complexity Wallace Multiplier
Inamul Hussain and Manish Kumar

Multiplier is the basic unit of any VLSI circuit. Wallace tree multiplier is the most popular multiplier architecture among various available multiplier architectures. Designers have designed the Wallace multiplier by using different approaches. In this paper a new approach is proposed to design a fast and reduced complexity Wallace multiplier. The proposed multiplier is found to be better in performance in terms of complexity, delay, and power delay product in comparison with a conventional Wallace multiplier and a reduced complexity Wallace multiplier. Delay and power delay product of the proposed 4×4 bit multiplier are 471.5ps and 1.563pJ respectively at 25MHz.

Keywords: Power, delay, power delay product, reduced complexity.

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