Design and Performance Analysis of AND-OR Gate Using Schmitt Trigger
Nilotpal Arjun, Ayushi Marwah and Shyam Akashe
AND/OR logic gate are the basic building block of every digital circuit. The paper utilizes Schmitt Trigger in design of AND/OR logic gate which helps in improvement of circuit performance. Large numbers of transition in output of these gates result in higher dissipation of power. Schmitt Trigger is used in place conventional NOT gate for improving the performance and output of the circuit. With the use of Schmitt Trigger in place of conventional NOT gate the hysteresis in the circuit is adjusted which leads to reduction of noise, decreasing the slew rate in the output, reduction in leakage power and improving delay in the circuitry. Noise in any circuit can change the output state and distort the information. The proposed design reduces noise and thus enhancing the performance of the circuit. Efficiency in the AND and OR Gate is improved to 34% and 50% from 29.5% and 40% respectively. Presented design shows improvement in leakage power dissipation as compared to conventional AND and OR based logic gate. The operating voltage is very low as compared to other circuits. The designing of the circuit is done in 45nm using Cadence Virtuoso tool and the circuit is simulated and result is obtained.
Keywords: AND/OR Gate, Schmitt Trigger, Hysteresis, Slew Rate, Efficiency