Design and Implementation of Pipelining Based Area Efficient Fast Multiplier
Ruby Jain and Vivek Jain
Optimization of a multiplier is a challenging task. A number of researchers have been tried to optimize the performance of multiplier but user still need more optimized multiplier. The multiplier is a key building block of any digital circuit or computing device. For advancement in the field of DSP,FFT and to improve performance of gadgets we need to have more faster and area efficient multiplier. Several multipliers architectures have been proposed previously, whenever optimization in area is done the time required is increased and vice versa. Here the pipeline-based architecture have been proposed to optimize both area and speed. The multiplier is simulated on quartusII.
Keywords: Multiplier, Shift and add