JAPED Home • Issue Contents

Design and Optimization of Multi-Gate Based Controlled Bridge Rectifier
Poonam Kiran Tiwari, Prateek Jain and Shyam Akashe

The present paper proposes a new Fin Field-Effect Transistor (FinFET) based bridge rectifier in which rectification is done using internal threshold cancellation (ITC) technique with the effect of an extra PMOS simulated between the four FinFETs which acts as the diodes in the circuit for the conversion of signals used in rectification process. FinFET provide the best alternative to the classical planner CMOS technology. The new circuit designed is very compact and reliable for the future uses of the devices as the greater efficiency is obtained. FinFET can improve the performance and extensively reduce the chip area. Although it is still in its infantry stages it has shown much capability to replace bulk CMOS, hence much research is being pursued in FinFET designs. The proposed circuit works on the concept of ITC (internal threshold cancellation) and with the limitations in performance. The proposed rectifier is designed and simulated in the cadence virtuoso tool in 45nm technology at 0.7v supply. Moreover, the simulation result indicates that the efficiency is improved, noise is reduced and voltage gain is greatly enhanced and the power consumption is also improved. Near about 96% efficiency is achieved in this proposed circuit as compared to its conventional circuit. The result in this work shown that the new circuit designed is very compact and reliable for the future uses of the device as the greater efficiency is obtained.

Keywords: CMOS, FinFET, ITC, Efficiency, noise, voltage gain, power consumption

Full Text (IP)