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Design and Optimization of 2:1 Multiplexer for Low-Power Applications
Mohit Vyas and Shyam Akashe

The purpose of this paper is to reduce power of 2:1 MUX. This paper describes the impact of logic style, that is, how it effects on MUX circuit. In this paper, MTCMOS technique has been introduced and his comparison on the basis of noise, power consumption, leakage current and power with conventional circuit. Digital circuit with high speed and low power are mandatory for any digital circuit. In any arithmetic circuit, MUX is the heart of the circuit shortened as MUX. It is the very important part of computing devices starting from convenient devices to supercomputers and more. MUX is basic circuit of any digital circuit. 2:1 MUX is a unidirectional device and used in many applications in which data must be sent from desired input to particular output. MUX is the main constituent which consists of CMOS (Complementary Metal Oxide Semiconductor) memory component and data control structures. The low-power consumption is one of the most important concerns of the system design. In high-speed applications, different styles are developed for low power designs. The proposed MUX works on supply voltage of 0.7V. The design and simulation of transmission based 2:1 MUX is done by using 45nm technology at cadence virtuoso version 6.1 platform.

Keywords: CMOS, MUX, Leakage Current, Leakage Power, Power Consumption

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