JAPED Home • Issue Contents

The Palliation of Low Leakage Multi-Fin Based Schmitt Trigger Using Self Controllable Voltage Level Technique
Mukesh Kumar Singh and Shyam Akashe

In modern VLSI system, low power consumption has greater significance on system performance. Therefore, for achieving low power devices we have to minimize the leakage power of the circuit up to a great extent. In modern VLSI system, Schmitt trigger plays an important role in various forms. The Schmitt trigger circuit is mainly cast off as the input circuit to protect in contradiction of noise persuaded false switching. In the voltage transfer curves they are having hysteresis by virtue of this induced hysteresis they are different from their counterparts. The Schmitt trigger hysteresis yield enhanced noise margin and noise stability as compared to the inverter. In the proposed Schmitt trigger circuit, we have implemented FinFET in the conventional Schmitt trigger circuit to optimize their various parameters such as noise, power consumption, leakage power and hysteresis. FinFET has shown tremendous impact in modern VLSI system. For auxiliary reducing the leakage power, noise and power consumption of the circuit we have applied valuable Self-controllable Voltage Level (SVL) technique on FinFET based Schmitt trigger. By applying the SVL technique, we get some significant changes in various parameters such as power consumption, total noise, leakage power, hysteresis width up-to a large extent. In deep submicron regimes leakage current is a chief sponsor in total power dissipation in a device. By the implementation of SVL technique we have achieved to reduce the power consumption by 86% of the proposed circuit. Meanwhile, the hysteresis width has been increased by 68%. In the proposed circuit the total noise has been decreased by 98% as compared to the conventional Schmitt trigger circuit. The leakage Power has been almost negligible for the proposed circuit which is 2.51 For conventional circuit and 71.5For the proposed circuit. The proposed circuit has been simulated in 45nm technology in the cadence virtuoso tool. The circuit has been operating at 0.7v power supply.

Keywords: Schmitt trigger, FinFET, Low Power, Hysteresis width, SVL Technique, Leakage Power

Full Text (IP)