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Performance Evaluation of Strained-Engineered Embedded-SiGe Source-Drain and SiGe Channel FinFETs
C. K. Maiti, T. P. Dash and S. Dey

In this work, performance analysis of strain-engineered FinFETs has been performed using simulation. The prospect of Silicon-Germanium (SiGe) as channel material has been explored for the introduction of SiGe-CMOS technology for FinFETs. The impact of Silicon-Germanium stressor in a SiGe-embedded source/drain FinFET structure is examined. As stress has a major impact on transistor characteristics in advanced devices, stress effects need to be determined from simulation in order to study the influence of stress-related effects. Through the use of the three-temperature dependent piezoresistive coefficients of silicon stress analyses have been performed and the results are presented. We have also investigated the effects of low temperature on the electrical performance of silicon FinFETs. The physics-based 3D device simulation tool VictoryDevice is used for the simulations and characterization of the electrical properties of strain-engineered SiGe-channel FinFETs. Performance enhancement is observed at low temperature.

Keywords: FinFET, low-temperature electronics, TCAD, Silicon-Germanium stressor, piezoresistive coefficients, SiGe-CMOS technology

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