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Design and Optimization of Power Efficient Shift Register Using Five-Transistor Based D-Flip flop
Harshit Singh, M. Meenalakshmi and Shyam Akashe

In this paper D-flip flop based shift register circuit is designed with low-power and low-delay. The proposed design of shift register used 5transistors based D-flip flop. The delay and power utilization of shift register are decreased by replacing 10 transistors based D flip-flops with 5 transistors based D flip-flops and having only one clock pulse. The shift register gives the reducing parameters such as power consumption, leakage power, noise and delay. For parameter calculation and simulation of the proposed design cadence virtuoso tool is used at 45nm technology and comparison of both conventional and proposed circuits is made. The design of proposed shift register reduces several parameters like noise, slew rate, power consumption, leakage power and delay at 0.7 V supply voltage. The designing of shift register at low power is used for several applications such as communication, image processing, multimedia system and electronic devices.

Keywords: Shift register, noise, power consumption, leakage power, delay

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