Design a Low-Power D Flip-Flop Using the 0.18 μm CMOS Technology
Suvigya Gupta and Nikhil Saxena
To structure a Low-Power D-Flip-Flop using the 0.18 μm CMOS Technique is introduced. This Low-Power D-Flip-Flop outline allowance decline force delay item and range of the circuit, while keeping up low various nature of explanation composition. Decaptation examination with other DFF outline actions is displayed, as for door territory, number of devices, defer and power discarding. A collection of circuits have been really used in 0.18μm changes to think about the developed CMOS structure the after effects of the interaction of delegate flip failures delineate the benefits of our methodology and the suitability of diverse configuration styles for superior and low-power applications. We have talked about and reenactment results are accounted for. We are utilizing Hspice programming.
Keywords: D-FF, CMOS Technology, power