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A 105-nW, 0.6-V Sub-Threshold Op Amp Using SDDG FinFET Transistors
Jainendra Tripathi, Ranjeet Singh Tomar and Shyam Akashe

In this paper, we present a Simultaneously Driven Double Gate (SDDG) FinFET based two stage sub-threshold op amp design in 45 nm FinFET technology. The output stage of the op amp is a class AB circuit. Instead of Miller compensation technique Indirect compensation (current buffer compensation) technique is used in the op amp design. Each FinFET device of the op amp is operated in sub-threshold. The op amp has a DC gain of 50.8dB and a Gain Bandwidth product equal to 140 kHz with a 15 pF load capacitor. The op amp has total power dissipation equal to 105.6nW.

Keywords: SDDDG, FinFET, Sub-Threshold operation, Indirect compensation, class AB output

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