Simulation and Verification of LECTOR 6T FinFET SRAM: A Low Leakage Cell
Shyam Sharma, Darpan Verma, Saurabh Khandelwal and Shyam Akashe
In this paper we introduced a technique named LECTOR that is applied to FinFET based 6T SRAM cell that significantly lowers the leakage current without hampering dissipated power which is dynamic in nature, rather decreases the dissipation and leakage current to great extent. Today there is a great demand of high performance and low leakage driven devices. Along with these features designers are plunging towards submicron level to manufacture high density devices. But all these design factors have led to increase in sub-threshold current, due to reduction of gate oxide thickness and hence power dissipation also increases. So, this paper presents the design and verification of conventional and LECTOR technique employed FinFET 6T SRAM cell at 0.6V, 0.7V and 0.8V in Cadence Virtuoso Tool at 45 nm technology. It is observed that leakage current reduces to 68.13 fA from 78.26 fA, and leakage power reduces to 8.239 nw from 10.25 nw at 0.7V that shows in our proposed technique we get 14 – 16 % less leakage current and 20 – 40 % less leakage power.
Keywords: 6T SRAM, LECTOR, leakage current, power dissipation