JAPED Home • Issue Contents

FPGA and ASIC Implementation of RS(47, 41) Codec for Intelligent Home Networking System
Jagannath Samanta, Jaydeb Bhaumik and Soma Barman

An intelligent home networking scheme is used for residential energy monitoring and controlling purposes. Various services within a home can be performed by employing a common communication system. In this system, noise occurs during the transmission of digital data through wire or wireless channel. Different error correcting coding techniques are employed to detect and correct the transmission errors. RS(47, 41) codes are popularly used to enhance the reliability of intelligent home networking system. In this paper, design and implementation of RS(47, 41) encoder and decoder have been described. The reformulated inversionless Berlekamp Massey algorithm (riBM) is used in ‘key equation solver’ block. The RS codec is simulated and synthesized using both FPGA and ASIC platforms. Complete simulation waveforms are shown for different blocks of RS codec. Also hardware complexity, operating frequency, delay and power consumption have been presented here.

Keywords: Intelligent home networking, Error correcting code, Reed-Solomon code, reformulated inversion-less Berlekamp Massey algorithm, VLSI, FPGA, ASIC.

Full Text (IP)