JAPED Home • Issue Contents

Novel Three Stage CMOS Ring Oscillator Circuit Design with Co-Integration of N-InGaAs and P-SiGe Vertical Nanowire Transistor Devices
Subha Subramaniam, Sangeeta M. Joshi and R. N. Awale

This paper presents the co-integration of InGaAs and SiGe based Vertical Nanowire Transistors (VNWT) into CMOS Ring oscillator via numerical simulation approach for the first time. N-In0.53Ga0.47As Vertical Nanowire Transistors and P-Si0.75Ge0.25 Vertical Nanowire Transistors are designed at 14nm gate length. A 3 stage CMOS Ring oscillator is designed using InGaAs N-VNWT and SiGe P-VNWT devices and a minimum of 66GHz oscillation frequency is obtained. The obtained simulation frequency is at par with the analytical frequency calculated. The proposed ring oscillator circuit is compared systematically with N type- InGaAs and P type-SiGe based horizontal Nanowire Transistor (HNWT) based ring oscillator circuit with the same numerical simulation approach. Our results prove that VNWT based ring oscillators shows 14% increase in oscillation frequency and 28% increase in amplitude in comparison with HNWT based CMOS ring oscillator circuit. Our results prove that the Vertical Nanowire Transistors are the suitable candidate for high frequency RF ring at ultra-short channel length up to 14nm.

Keywords: Vertical nanowire, VNWT, ring oscillator, RF frequency, HNWT

Full Text (IP)