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FPGA and ASIC Implementation of Different Finite Field Multipliers for Forney Block
Tarique Hassan, Jagannath Samanta and Jaydeb Bhaumik

Finite or Galois field arithmetic is popularly employed to describe several algorithms in error control coding, cryptography and digital signal processing. Addition and multiplication are the two basic operations in finite field. Galois field addition operation is simpler whereas multiplication is complex and time-consuming operation. Other complex arithmetic operations like exponentiation, multiplicative inversion and division which are generally computed by employing multiplication as the basic operation. Design and efficient implementation of finite field multiplier is important to optimize area, delay and power. In this paper, five different architectures of finite field multipliers are designed over GF(28). These multipliers are simulated and synthesized using both Field Programmable Gate Array and Application Specific Integrated Circuit tools. Synthesis results of all designs are compared in terms of area, delay and power. Finally parallel and systolic multipliers are used in the Forney block of Reed Solomon decoder and synthesis results are also reported.

Keywords: Galois field, finite field multiplier, Reed Solomon code, Forney block, FPGA, ASIC

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