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Analysis of Static Noise Margin in 6T Sram Cell At 45 And 32 NM Technology
Garima Upadhyay, Amit Singh Rajput and Nikhil Saxena

SRAM Memory cell stability is a critical issue in scales technology. Memory cell suffered from the low stability problem at nanometer technology. Stability of memory cell against noise generally measured by a parameter called SNM. This paper analyzes read operation in static noise margin (SNM) of 6T SRAM cell and presents its stability variation with cell ratio (CR), pull-up-ratio (PR), temperature and power supply at 32nm and 45nm CMOS technology. This work uses a most popular butterfly method for SNM calculation of 6T memory cell. Simulation result indicates that the read SNM was 0.226v at nominal supply with a minimum size transistor in 45nm technology, which was 58% higher than 32nm technology in conventional 6T SRAM memory cell. The experimental results indicate that the value of SNM is reduced as technology scale down in 6T SRAM cell. Simulation was performed by Hspice using 32 nm and 45 nm PTM model.

Keywords: SRAM, static noise margin, butterfly curve, cell ratio, pull-up-ratio

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